Intel Nova Lake vs. Zen 6: Last-Level Cache Battle for Next-Gen CPU Performance

Intel’s expanding last-level cache architecture shapes upcoming competition with AMD’s stacked-cache Zen processors across gaming workloads.

Hardware by Godrics01 on Nov 27, 2025

Nova Lake is rumoured to come out next year, in 2026. It is set to have 52 cores: 16 P-cores, 32 E-cores, and four low-power E-cores, for a total of 52 cores and 52 threads. There is no hyper-threading. We are not as interested in the top-end skew today. What matters is Intel's counter to X3D.

High Yield's video on Clearwater Forest showed official Intel slides noting a large last-level cache on the compute tile. Out of 24 E-cores, 48 MB of large last-level cache was available. The active base tiles change things. Previous base tiles were silicon interposers connecting the chip.

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This active base tile still does that, but adds cache on top. That is where the potential for large cache expansion begins. Clearwater Forest uses a silicon interposer built on Intel 3, not an older node. This interposer includes large amounts of cache: around 144 MB per tile and around 500 MB across the whole chip. That structure is where future CPUs may move.

Nova Lake BLLC Expectations

The first rumoured chip is Nova Lake, a large last-level cache design. This cache is not on the silicon interposer but added directly to the compute die. It is not 3D stacked. The compute die includes approximately 144 MB of large last-level cache.

The chip includes 8 P-cores, 16 E-cores, and four low-power E-cores for a total of 28 cores, of which around 24 are practical. Past estimates put performance around 30% faster than Arrow Lake, placing it at a 9800X3D level. With overclocking and IPC scaling, it could be around 10% faster, but more realistically around that 9800X3D range. It will also have multi-core performance 20%-30% above 285K and include an iGPU.

Dual-BLLC Nova Lake Scenario

Intel could go further with dual BLLC dies. That would be one chip with BLLC and another chip with BLLC. That would be a large cache volume and 52 cores with extra cache. Some claim 180MB total instead of 144MB doubled. If doubled, it would be 288MB.

That is significant. This could deliver higher multi-core capability and consistent gaming behaviour since both tiles have cache, avoiding the split behaviour seen in something like the 9950X3D. A chip like this would likely cost more than $1,000; for some users, that may be acceptable given the hardware involved.

Zen 6 X3D Direction

Zen 6X3D is expected to have 96MB of stacked cache plus 48MB of L3 cache on the CCD for a 12-core design. That gives 12 P-cores with cache volume and expected high clock speeds. Comparing that to a 28-core Nova Lake BLLC tile shows different strengths.

AMD's architecture has matured with chiplets. Their interposer quality matters, and it has been rumoured that they may use the same interposer as Strix Halo. Expectations place a 10800X3D around 20–25% above a 9800X3D. That may put AMD around 10–20% ahead of Intel in gaming.

Intel may struggle with latency because Nova Lake places the memory controller off-die. AMD already addresses that challenge, and its refinement may help it maintain an advantage. Out of the box, the 12-core Ryzen CPU with multi-threading (24 threads) may outperform Intel's 8 P-core tile with only eight threads. That may influence results.

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Nova Lake As A Workstation Platform

Nova Lake's purpose is not gaming alone. With 52 cores and platform expansion, it is intended as a workstation system. It may support 36 PCIe Gen5 lanes, giving 16 for GPU and 20 for NVMe. Assuming 4 for the chipset leaves 16 for storage, enough for 4 Gen5 NVMe drives.

It may also include 16 PCIe Gen4 lanes for four more NVMe drives. Eight NVMe drives at 4TB each yield 32TB of storage capacity. Users who need workstation capabilities without the high cost of workstation boards can utilise this. Motherboards may be around $400–$500, but the platform flexibility is wide.

A dual-BLLC 52-core Nova Lake chip could serve as a long-term platform for many years. A 12-core X3D chip may have gaming strength, but far fewer threads for future workloads.

Titan Lake And Active Base Tile Cache Potential

Morse Law is Dead; once discussed ELLLC, a 3D-stacked cache planned for Titan Lake. That was scrapped. Comparing that to High Yield's active base tile concept suggests a potential replacement. If Titan Lake integrates a silicon interposer on Intel 3 with around 100MB of cache and uses smaller compute dies for cores.

Intel could add more cores, possibly around 82 cores. The active cache interposer, acting as a communication layer, is where the architectural shift may occur. That direction is where cache expansion could dominate.

Intel, Nova Lake, Zen 6, Last-Level Cache Battle, Next-Gen CPU Performance, NoobFeed

Final Thoughts

CPU competition is shifting quickly. Intel is investing in new architectures. AMD is advancing its I/O and gaming designs. Intel is developing a consumer HEDT-like platform with Nova Lake and may regain performance leadership if an active base tile cache appears by Titan Lake.

Right now, users can hold off on upgrades and wait for Nova Lake or Zen 6. These architectures are expected to be large jumps beyond Zen 5 and Arrow Lake. GPUs are currently stable in price and may increase soon, so upgrading a GPU makes more sense than upgrading a CPU.

Concerns remain since products built on 2nm could face delays. DDR prices are rising in the US, making launches difficult. SK Hynix is working on LPDDR6 at 14000 MT/s and GDDR7 at 48 Gbit/s, far above the current 28 Gbit/s. The market is shifting quickly with AI pushing development. The hope is that consumer hardware remains available and not deprioritised.

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